The present invention relates generally to the field of microprocessors and computer systems. More particularly, the present invention relates to a method and apparatus for an adaptive variable frequency clock system for microprocessors.
In recent years, the price of personal computers (PCs) have rapidly declined. As a result, more and more consumers have been able to take advantage of newer and faster machines. Computer systems have become increasingly pervasive in our society. But as the speed of the new processors increases, so does the power consumption. Furthermore, high power consumption can also lead to thermal issues as the heat has to be dissipated from the computer system.
One attempt to reduce power consumption entails the use of low power circuit devices. Another power saving method is to use software in controlling system power and shutting down system devices that are not needed. Several voltage/frequency adjustment schemes including Intel(copyright) SpeedStep(trademark) technology have been developed to maximize battery life for mobile processors.
But even as designers slowly reduce the power needs of the overall system, the power requirements of the processor have often remained steady. Furthermore, existing schemes are usually targeted at mobile products. Present methods that implement deep processor operating frequency reductions do so by adjusting the bus ratios. Such methods are not feasible in a server or desktop product because of the significant performance impact.
A high clock frequency is one of the principal performance drivers for a high performance microprocessor design. Thus one common method for achieving higher performance is to increase the processor operating frequency. Frequency gains can be attained through techniques such as technology scaling, advanced pipelining and circuit optimizations. As a result, processors with operating frequencies approaching or exceeding 2 gigahertz (GHz) are on the near horizon. But one significant drawback of this current trend is the increase in power dissipation. As the performance trend continues, thermal and power delivery constraints will become a significant hurdle in the development of future high performance multi-GHz processors. Power is linearly proportional to the operating frequency (i.e. Powerxe2x88x9dFrequency*Voltage2). Thus power dissipation can be lowered by decreasing the operating frequency at selected times.
FIG. 1 is block diagram of a typical prior art microprocessor clock generator circuit architecture. The processor 100 includes a clock generator 102 and a front side bus (FSB) unit 138. Clock generator 102 provides an internal processor clock to the processor core 136 and to the FSB unit 138. The clock generator 102 comprises a phase locked loop (PLL) 108, ring oscillator 114, and a feedback network. The on-chip PLL 108 multiplies the frequency of the system clock 104 to generate the on-chip core clock (Core Clock) 120. The core to system clock frequency multiplication factor is determined by the bus fraction ratio N, where N greater than 1 and typically between 10 and 30. The bus fraction ratio N is normally set to a constant for most microprocessor systems.
Frequency/voltage adjustment methods can be used to control power consumption. However, modifications to the core clock signal during processor operation can cause errors to the system. Typically, existing frequency adjustment schemes need to stop or pause the processor core before adjusting the clock frequency or modifying the bus ratio. Frequencies are changed in a clocked device by placing the device in an idle state, changing the core clock frequency to the new frequency, and locking the PLL in phase with the new frequency. The length of the idle state required for the changing and locking to occur slows down the system. Such a pause can have a significant impact on the overall performance of a desktop or server.